Toward a Software Pipelining Framework for Many-core Chips

Current trends in high performance computing have produced two distinct families of chips. The first one is called complex core, which consists of a few, very architecturally sophisticated cores. The other chip family consists of many simple cores, which lack the advanced features of the complex ones. The two ideological camps have their examples in the current market. The Intel Core Duo family and start-up efforts, like the Tilera 64 chip, are the vanguards for each camp. Currently, complex cores have an advantage over the simple ones due to the fact that most of the system software and applications are written for sequential machines. Moreover, several compiler techniques are stagnant due to its sequential focus point. The rise of complex and simple cores are disturbing the compiler research field and brought back problems which have been ignored for more than three decades. The major performance objectives for optimizing compilers have been, and still are, loops. Among the most known and researched loop scheduling techniques is software pipelining. Due to the rise of simple cores, many of the hardware features, which supported more advanced software pipelining techniques, have been sacrificed in the battle for more cores. Due to the comeback of the simple cores, we have to rely on the original software pipelining techniques, which were developed over two decades ago. The software pipelining framework described in this thesis does not rely on any special hardware support. It was implemented in PathScale’s EKOPath compiler for the SiCortex Multiprocessor architecture. The experimental results show